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Description
As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple’s silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple’s DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems.
Minimum Qualifications
Minimum of BS degree + 3 years of relevant experience Python programming background
Preferred Qualifications
Experience debugging vendor tool problems Experience developing, maintaining, and enhancing an existing system for regressing RTL Experience with TCL or Perl is a plus Experience with artificial intelligence and machine learning Experience with interacting with DV team(s) to help solve their problems. Experience in implementing new functionality to solve emerging problems or to optimize already existing methods. MSEE/CE/CS preferred Knowledge in Verilog and SystemVerilog; familiarity with VHDL a plus Experience with Synopsys VCS, XCelium, or Modelsim Good communications skills are required and prior customer support experience is a plus Experience writing or maintaining a script or Makefile that builds a simulation model from RTL is a plus Familiarity with Verdi and/or Indago is considered a plus Knowledge of C and C++ is a plus
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