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Description
As a key member of our industry-leading team, you will drive the evolution of our RF receiver architectures. You will influence and collaborate with RF circuit design, platform architecture, and software engineering teams to define and implement concepts that deliver uncompromising performance and quality.
Minimum Qualifications
BSEE required. Demonstrated System Engineering experience in designing complex communication RF systems (e.g. Cellular, WiFi), with deep expertise in state-of-the-art receiver architectures. Demonstrated ability to influence and drive innovation and execution excellence across an organization.
Preferred Qualifications
5 years of experience in Radio Receiver design is preferred. Deep understanding of cellular system use cases, transmit/receive interactions, and coexistence challenges in complex consumer electronics. Experience in clock/frequency planning. Good understanding of BB related algorithms/aspects (e.g. channel estimation/equalization). Good understanding of analog data converters, from a system perspective/impairments. Experience applying artificial intelligence (AI) or machine learning (ML) to enhance multi-objective optimization of the RF line-up and link budget models. Deep theoretical and practical understanding of RF system performance metrics and impairments (NF, non-linearity, phase noise, IQ imbalance, DC) and their direct impact on overall system performance. In-depth understanding of 3GPP standards with a focus on RF requirements and physical layer procedures for FR1 and FR2. Proficiency in using MATLAB and Python for RF system modeling and simulations. Strong analytical and problem-solving skills, with the ability to communicate complex technical concepts effectively to diverse, cross-functional global teams. Mastery of RF line-up analysis and detailed development of a level plan for modern receiver architecture. Experience with lab bring-up, system calibration, and debugging RF Familiarity with modern digital modem architectures. Familiarity with RFIC design, layout considerations, and semiconductor processes.
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