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  3. SoC Physical Design Engineer, STA/Timing

SoC Physical Design Engineer, STA/Timing

Apple
Posted 2 months ago, valid for 24 days
Location

Waltham, MA 02454, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • Apple is seeking a highly experienced professional with a minimum of 10 years in the industry for a role focused on the physical implementation of design partitions for complex SoCs.
  • The position requires strong programming skills, particularly in TCL, and experience with large design STA and timing closure is preferred.
  • Candidates should possess a deep understanding of timing modeling effects, including noise and crosstalk, as well as circuit modeling and SPICE simulation.
  • The role involves collaboration with design teams to debug constraints and improve timing, as well as creating documentation and methodologies for analysis.
  • The salary for this position is competitive, reflecting the candidate's extensive experience and expertise in the field.
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product. In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.

Description


- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing. - Work with the Physical Design team, highlighting issues and best practices. - Help create timing ECO’s for project tapeout. - Create and maintain scripts and methodologies for analysis and runs. - Create documentation and help with guidelines/specs. - Deep analysis of timing paths to identify key issues. - Implement timing infrastructure.

Minimum Qualifications


Minimum BS and 10+ years of relevant industry experience Strong programming skills with TCL

Preferred Qualifications


Experience with large design STA and/or Timing Closure. Experience with timing of large high-performance SoC designs in sub-micron technologies. Deep understanding of noise, crosstalk, OCV and other timing modeling effects. Knowledge of circuit modeling including timing models, worst-case timing corner selection, and SPICE simulation. Experience in ECO techniques and implementation. Experience with other scripting languages such as Perl or python. Good communicator who can accurately describe issues, propose solutions, and drive them through completion.


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