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Verification Engineer

Platform Recruitment
Posted 10 hours ago, valid for 8 days
Location

Cambridge, Cambridgeshire CB2 8AG, England

Contract type

Full Time

In order to submit this application, a Reed account will be created for you. As such, in addition to applying for this job, you will be signed up to all Reed’s services as part of the process. By submitting this application, you agree to Reed’s Terms and Conditions and acknowledge that your personal data will be transferred to Reed and processed by them in accordance with their Privacy Policy.

Sonic Summary

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  • Join an innovative company leading the RISC-V revolution, focusing on high-impact applications in machine learning, aerospace, and automotive.
  • The position offers a flat structure with a diverse workload and excellent benefits.
  • As a Senior Verification Engineer, you will develop and maintain verification infrastructure, define verification strategies, and manage coverage metrics.
  • Candidates should have strong proficiency in SystemVerilog and UVM, along with substantial experience in verification methodologies and a solid understanding of mixed hardware/software approaches.
  • A minimum of 5 years of experience is required, and the salary is competitive based on qualifications.

Join an innovative, rapidly expanding company at the forefront of the RISC-V revolution developing IC that has high-impact applications across machine learning, aerospace and automotive.

Flat structure with a highly diverse workload and excellent benefits.

Senior Verification Engineer

Responsibilities:

  • Develop and maintain verification infrastructure in collaboration with design teams and external partners.
  • Define and implement detailed verification strategies and architectures to ensure product quality and performance.
  • Manage functional and code coverage metrics to track and report progress.
  • Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests.

Requirements:

  • Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies.
  • A solid understanding of mixed hardware/software verification approaches.
  • Experience with RISC-V architectures is preferred.
  • Proven ability to work effectively with design teams and external partners to achieve project goals.

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In order to submit this application, a Reed account will be created for you. As such, in addition to applying for this job, you will be signed up to all Reed’s services as part of the process. By submitting this application, you agree to Reed’s Terms and Conditions and acknowledge that your personal data will be transferred to Reed and processed by them in accordance with their Privacy Policy.